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june 2011 doc id 18094 rev 2 1/24 24 L6230 dmos driver for three-phase brushless dc motor features operating supply voltage from 8 to 52 v 2.8 a output peak current (1.4 a rms) r ds(on) 0.73 typ. value @ t j = 25 c integrated fast free wheeling diodes operating frequency up to 100 khz non dissipative overcurrent detection and protection cross conduction protection diagnostic output uncommitted comparator thermal shutdown under voltage lockout application bldc motor driving sinusoidal / 6-steps driving field oriented control driving system description the L6230 is a dmos fully integrated three- phase motor driver with overcurrent protection, optimized for foc application thanks to the independent current senses. realized in bcdmultipower technology, the device combines isolated dmos power transistors with cmos and bipolar circuits on the same chip. an uncommitted comparator with open-drain output is available. available in powerso36 and vfqfpn-32 5x5 packages the L6230 features a non dissipative overcurrent protection on the high side power mosfets and thermal shutdown. vfqfpn32 powerso36 table 1. device summary order codes package packaging L6230pd powerso36 tube L6230pdtr tape and reel L6230q vfqfpn32 tube L6230qtr tape and reel www.st.com
contents L6230 2/24 doc id 18094 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 non-dissipative overcurrent detection and pr otection . . . . . . . . . . . . . . . 13 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 field oriented control driving method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 six-step driving method with current control . . . . . . . . . . . . . . . . . . . . . . 16 6.3 six-step driving method with bemf zero crossing detection . . . . . . . . . . 17 6.4 thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
L6230 block diagram doc id 18094 rev 2 3/24 1 block diagram figure 1. block diagram &+$5*( 3803 92/7$*( 5(*8/$725 7+(50$/ 3527(&7,21 2&' 2&' 2&' 9 9 9&3 96 $ *$7( /2*,& 9%227 9 %227 287 287 6(16( 96 % 287 6(16( ',$*(1 ,1 ,1 (1 (1 &3 ,1 2&' 9 %227 2&' 9 9 %227 2&' 9 9 %227 2&' 9 &203$5$725 &3 &3287 6(16( (1
electrical data L6230 4/24 doc id 18094 rev 2 2 electrical data 2.1 absolute maximum ratings 2.2 recommended operating conditions table 2. absolute maximum ratings symbol parameter parameter value unit v s supply voltage vsa = vsb = v s 60 v v od differential voltage between: vsa, out1, out2, sensea and vsb, out3, senseb vsa = vsb = v s = 60 v; v sensex = gnd 60 v v boot bootstrap peak voltage vsa = vsb = v s v s + 10 v v in , v en logic inputs voltage range -0.3 to +7 v v cp- , v cp+ voltage range at cp- and cp+ pins -0.3 to +7 v v sense voltage range at sensex pins -1 to +4 v i s(peak) pulsed supply current (for each vs pin) vsa = vsb = v s ; t pulse < 1 ms 3.55 a i s rms supply current (for each vs pin) vsa = vsb = v s 1.4 a t stg , t op storage and operating temperature range -40 to 150 c table 3. recommended operating conditions symbol parameter parameter min max unit v s supply voltage vsa = vsb = v s 8 52 v v od differential voltage between vsa, out1a, out2a, sensea and vsb, out1b, out2b, senseb vsa = vsb = v s ; v sense1 = v sense2 = v sense3 52 v v cp- , v cp+ voltage range at cp- and cp+ pins -0.1 5 v v cpcm common mode voltage at the comparator inputs 03v v sense voltage range at pins sensex pulsed t w < t rr -6 6 v dc -1 1 v i out rms output current 1.4 a t j operating junction temperature -25 +125 c f sw switching frequency 100 khz
L6230 electrical data doc id 18094 rev 2 5/24 2.3 thermal data table 4. thermal data symbol parameter value unit powerso36 qfn32 r th(j-amb)1 maximum thermal resistance junction-ambient (1) 1. mounted on a multi-layer fr4 pcb with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m). 36 - c/w r th(j-amb)1 maximum thermal resistance junction-ambient (2) 2. mounted on a multi-layer fr4 pcb with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m), 16 via holes and a ground layer. 16 - c/w r th(j-amb)2 maximum thermal resistance junction-ambient (3) 3. mounted on a multi-layer fr4 pcb without any heat-sinking surface on the board. 63 - c/w r th(j-amb)3 maximum thermal resistance junction-ambient (4) 4. mounted on a double-layer fr4 pcb with a dissipating copper surface of 0.5 cm 2 on the top side plus 6 cm2 ground layer connected through 18 via holes (9 below the ic). -42c/w
pin connection L6230 6/24 doc id 18094 rev 2 3 pin connection figure 2. pin connection powerso36 (top view) figure 3. pin connection vfqfpn32 (top view) note: the pins 2 to 8 are connected to die pad. the die pad must be connected to gnd pin. '.$ . # .# 63! #0 /54 . # .# . # .# .# $)!'%. #0/54 . # 63" . # .# '.$ '.$ '.$ %. 3%.3% ). 3%.3% %. ). ). #0 /54 3%.3% 6#0 %. /54 6"/ /4 .# . # 0owe r3/ 4heslugisinternallyconnected topinsand'.$pins '.$ 6#0 /54 63! '.$ 63" /54 .# 6"//4 .# .# .# .# .# .# .# $)!'%. .# #0/54 ). %. #0 %. 3%.3% .# /54 #0 ). %. ). 3%.3% 3%.3% 6&1&0.
L6230 pin connection doc id 18094 rev 2 7/24 table 5. pin description pin type function vboot power supply bootstrap voltage needed for driving the upper power mosfets. vcp output charge pump oscillator output. diag-en logic output/input double function: chip enable as input and overcurrent/over-temperature indication as output. low logic level switches off all power mosfets, putting the power stages in high impedance status. an internal open drain transistor pulls to gnd the pin when an overcurrent on one of the high side mosfets is detected or during thermal protection. in1 logic input logic input half bridge 1. en1 logic input enable input half bridge 1. in2 logic input logic input half bridge 2. en2 logic input enable input half bridge 2. in3 logic input logic input half bridge 3. en3 logic input enable input half bridge 3. cp- analog input inverting input of internal comparator. cp+ analog input non-inverting input of internal comparator. cpout output open-drain output of internal comparator. sense3 half bridge 3 source pin. this pin must be connected to power ground through a sensing power resistor. out3 power output output half bridge 3. vsb power supply half bridge 3 power supply voltage. it must be connected to the supply voltage together with pin vsa. sense2 half bridge 2 source pin. this pin must be connected to power ground through a sensing power resistor. out2 power output output half bridge 2. sense1 half bridge 1 source pin. this pin must be connected to power ground through a sensing power resistor. out1 power output output half bridge 1. vsa power supply half bridge 1 and half bridge 2 power supply voltage. it must be connected to the supply voltage together with pin vsb. gnd ground ground terminal.
electrical characteristics L6230 8/24 doc id 18094 rev 2 4 electrical characteristics (v s = 48 v, t a = 25 c, unless otherwise specified) table 6. electrical characteristics symbol parameter test condition min typ max unit v sth(on) turn-on threshold 5.8 6.3 6.8 v v sth(off) turn-off threshold 5 5.5 6 v i s quiescent supply current all bridges off; t j = -25 c to 125 c (1) 510ma t j(off) thermal shutdown temperature 165 c output dmos transistors r ds(on) high-side / low-side switch on resistance t j = 25 c 0.73 0.85 t j =125 c (1) 1.18 1.35 i dss leakage current diag-en = low; out = v s 2ma diag-en = low; out = gnd -0.3 ma source drain diodes v sd forward on voltage i sd = 1.4 a, diag-en = low 1.15 1.3 v t rr reverse recovery time i f = 1.4 a 300 ns t fr forward recovery time 200 ns logic inputs (inx, enx, diag-en) v il low level logic input voltage 0.8 v v ih high level logic input voltage 2 v i il low level logic input current gnd logic input voltage -10 a i ih high level logic input current 7 v logic input voltage 10 a switching characteristics t d(on)en enable to output turn-on delay time (2) i load = 1.4 a, resistive load 500 650 800 ns t d(off)en enable to output turn-off delay time (2) 500 1000 ns t d(on)in other logic inputs to out turn-on delay time 1.6 s t d(off)in other logic inputs to out turn-off delay time 800 ns t rise output rise time (2) 40 250 ns t fall output fall time (2) 40 250 ns t dt dead time 0.5 1 s f cp charge pump frequency t j = -25 c to 125 c (1) 0.6 1 mhz
L6230 electrical characteristics doc id 18094 rev 2 9/24 figure 4. switching char acteristic definition comparator v offset offset voltage v cp- = 0.5 v -14 +14 mv t prop propagation delay (3) 500 ns i bias inputs bias current 10 a r cpout open drain on resistance 40 60 over current detection and protection i sover supply overcurrent protection threshold t j = -25 to 125 c (1) 2 2.8 3.55 a r diag open drain on resistance i diag = 4 ma 40 60 t ocd(on) ocd turn-on delay time (4) i diag = 4 ma; c diag < 100 pf 200 ns t ocd(off) ocd turn-off delay time (4) i diag = 4 ma; c diag < 100 pf 100 ns 1. tested at 25 c in a restricted r ange and guaranteed by characterization 2. see figure 4 . 3. measured applying a voltage of 1 v to pin cp + and a voltage drop from 2 v to 0 v to pin cp-. 4. see figure 5 . table 6. electrical characteristics (continued) symbol parameter test condition min typ max unit v th(on) v th(off) 90% 10% diag-en i out t t t fall t d(off)en t rise t d(on)en d01in1316
electrical characteristics L6230 10/24 doc id 18094 rev 2 figure 5. overcurrent de tection timing definition i sover 90% 10% i out v diag-en t ocd(off) t ocd(on) d02in1387 on off bridge
L6230 circuit description doc id 18094 rev 2 11/24 5 circuit description 5.1 power stages and charge pump the L6230 integrates a three-phase bridge, which consists of 6 power mosfets connected as shown on the block diagram (see figure 1 ), each power mos has an r ds(on) = 0.73 (typical value @ 25 c) with intrin sic fast freewheeling diode. cross conduction protection is implemented by using a dead time (t dt = 1 s typical value) set by internal timing circuit between the turn off and turn on of two power mosfets in one leg of a bridge. pins vs a and vs b must be connected together to the supply voltage (v s ). using n-channel power mos for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. the bootstrapped supply (v boot ) is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in figure 6 . the oscillator output (pin vcp) is a square wave at 600 khz (typically) with 10 v amplitude. recommended values/part numbers for the charge pump circuit are shown in ta b l e 7 . figure 6. charge pump circuit table 7. charge pump external component values component value c boot 220 nf c p 10 nf d1 1n4148 d2 1n4148 d2 c boot d1 c p v s vs a vcp vboot vs b
circuit description L6230 12/24 doc id 18094 rev 2 5.2 logic inputs pins inx and enx are ttl/cmos and microcontroller compatible logic inputs. the internal structure is shown in figure 7 . typical value for turn-on and turn-off thresholds are respectively v th(on) = 1.8 v and v th(off) = 1.3 v. pin diag-en has identical input structure with the exception that the drain of the overcurrent and thermal protection mosfet is also connected to this pin. due to this connection some care needs to be taken in driving this pin. the en input may be driven in one of two configurations as shown in figure 8 or figure 9 . if driven by an open drain (collector) structure, a pull-up resistor r en and a capacitor c en are connected as shown in figure 8 . if the driver is a standard push-pull structure the resistor r en and the capacitor c en are connected as shown in figure 9 . the resistor r en should be chosen in the range from 2.2 k to 180 k . recommended values for r en and c en are respectively 10 k and 5.6 nf. more information on selecting the values is found in the overcurrent protection section. figure 7. logic inputs internal structure figure 8. pin diag-en open collector driving figure 9. pin diag-en push-pull driving 5v d01in1329 esd protection 5v 5v open collector output r en c en diag-en d01in133 0 esd protection 5v push-pull output r en c en diag-en d01in1331 esd protection
L6230 circuit description doc id 18094 rev 2 13/24 5.3 non-dissipative overcurrent detection and protection the L6230 integrates an overcurrent detection circuit (ocd) for full protection. this circuit provides output-to-output and output-to-ground short circuit protection as well. with this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. figure 10 shows a simplified schematic for the overcurrent detection circuit. to implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power mos. since this current is a small fraction of the output current there is very little additional power dissipation. this current is compared with an internal reference current i ref . when the output current reaches the detection threshold (typically i sover = 2.8 a) the ocd comparator signals a fault condition. when a fault condition is detected, an internal open drain mos with a pull down capability of 4 ma connected to pin diag is turned on. the pin diag-en can be used to signal the fault condition to a c and to shut down the three-phase bridge simply by connecting the pin to an external r-c (see r en , c en ). figure 10. overcurrent protection simplified schematic figure 11 shows the overcurrent detection operation. the disable time t disable before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. it is affected whether by c en and r en values and its magnitude is reported in figure 12 . the delay time t delay before turning off the bridge when an overcurrent has been detected depends only by c en value. its magnitude is reported in figure 13 c en is also used for providing immunity to pin diag\en against fast transient noises. therefore the value of c en should be chosen as big as possible according to the maximum tolerable delay time and the r en value should be chosen according to the desired disable time. the resistor r en should be chosen in the range from 2.2 k to 180 k . recommended values for r en and c en are respectively 100 k and 5.6 nf that allow obtaining 200 s disable time. + over temperature i ref i ref i 1 +i 2 / n i 1 / n high side dmos power sense 1 cell power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells power dmos n cells high side dmos high side dmos out 1 out 2 vs a out 3 vs b i 1 i 2 i 3 i 2 / n i 3 / n ocd comparator to gate logic internal open-drain r ds(on) 40 typ. c en r en diag\ en v dd c or logic d02in1381
circuit description L6230 14/24 doc id 18094 rev 2 figure 11. overcurrent protection waveforms figure 12. t disable versus c en and r en figure 13. t delay versus c en i sover i out v th(on) v th(off) v en(low) v dd t ocd(on) t d(on)en t en(fall) t en(rise) t disable t delay t ocd(off) t d(off)en diag-en bridge on off ocd on off d02in1383 1 10 100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k r en = 100 k r en = 47 k r en = 33 k r en = 10 k 1 10 100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k r en = 100 k r en = 47 k r en = 33 k r en = 10 k 110100 0.1 1 10 cen [nf] tdelay [ s]
L6230 application information doc id 18094 rev 2 15/24 6 application information some typical applications using L6230 are shown in this paragraph. a high quality ceramic capacitor (c 2 ) in the range of 100 nf to 200 nf should be placed between the power pins vs a and vs b and ground near the L6230 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. the capacitor (c en ) connected from the diag-en input to ground sets the shut down time when an over current is detected (see overcurrent protection). the current sensing inputs (sense x ) should be connected to the sensing resistors r sense with a trace length as short as possible in the layout. the sense resistors should be non-inductive resistors to minimize the di/dt transients across the resistors. to increase noise immunity, unused logic pins are best connected to 5 v (high logic level) or gnd (low logic level) (see pin description). it is recommended to keep power ground and signal ground separated on pcb. the examples reported describe some typical application to drive a 3-phase bldc motor using L6230 device. in the first example is shown a field oriented control (foc) system, with this method it is possible to provide smooth and precise motor control of bldc motors. a six-step driving method with current control is reported in the second example, the inputs sequence is generated by external controller and the L6230 comparator is used to obtain the information for the peak current control. finally, the third example shows how to implement a sensorless motor control system, the information on rotor position is achieved by bemf zero-crossing detection. 6.1 field oriented co ntrol driving method in this configuration (see figure 14 ) three sensing resistors are required, one for each channel. the sensing signals coming from the output power stage are conditioned by external operational amplifiers which provide the proper feedback signals to the atod converter and the system controller. according to the feedback signals the six input lines are generated by the controller. note that some filtering and level shifting rc networks should be added between the sense resistor and the correspondent op-amp input. table 8. component values for typical application component value c 1 100 f c 2 100 nf c boot 220 nf c en 5.6 nf c p 10 nf d 1 1n4148 d 2 1n4148 r en 100 k
application information L6230 16/24 doc id 18094 rev 2 the uncommitted internal comparator with open-drain output is available. figure 14. f.o.c. typical application 6.2 six-step driving method with current control in this configuration only one sense resistor are needed, the three out pins are connected together to r sense (see figure 15 ). the non-inverting input comparator cp+ monitors the voltage drop across the external sense resistor connected between the source of the three lower power mos transistors and ground. as the current in the motor increases the voltage across the r sense increases proportionally. when the voltage drop across the sense resistor becomes greater than the reference voltage applied at inverting input cp- the comparator open-drain output is switched on pulling down the cpout pin. this signal could be managed by controller to generate the proper input sequence for six- step driving method with current control and select what current decay method to implement. when the sense voltage decrease below the cp- voltage, the open-drain is switched off and the voltage at cpout pin start to increase charging the capacitor c3. the reference volt age at pin cp- will be set according to sense resistor value and the desired regulated current (v cp- { r sense x i ta r g e t ). a very simple way to obtain variable voltage is to low-pass filter a pwm output of a controller. %. /54 #0 #0 '.$ #0/54 /54 /54 63 ! 0/7%2 '2/5.$ 3)'.!, '2/5.$ 6 3 6 $# 63 " 6#0 6"//4 # 0 # "//4 $ $ # # 3%.3% 2 3%.3% $)!'%. # %. 2 %. %.!",% ). %. ). %. ). %. ). %. ). %. ). 3%.3% 3%.3% 4(2%% 0(!3% -/4/2 - 2 3%.3% 2 3%.3% 4jhobmdpoejujpojoh "%$
L6230 application information doc id 18094 rev 2 17/24 figure 15. six-step with current control typical application 6.3 six-step driving method with bemf zero crossing detection the bemf zero crossing information can be used to evaluate the rotor position; in this way no hall effect sensors or encoder are needed. in six-step driving mode one of the three phases is left in high impedance state. comparing the voltage of this phase with the center-tap voltage we can detect the bemf zero-crossing. in shown example (see figure 16 ), the out1 phase voltage is monitored by the cp+; the center-tap voltage is obtained as combination of three phase voltages and monitored by the cp- pin. only when the out1 is in high impedance, the cpout will perform a commutation each time a bemf zero crossing is detected. in this configuration one sense resistor is needed, the three out pins are connected together to r sense . %. /54 #0 #0 '.$ #0/54 /54 /54 63 ! 0/7%2 '2/5.$ 3)'.!, '2/5.$ 07- fromcontroller 6 3 6 $# 63 " 6#0 6"//4 # #0 2 #0 # #0/54 2 #0/54 # "//4 $ $ # 3%.3% 2 3%.3% $)!'%. # %. 2 %. %.!",% ). %. ). %. ). %. #urrentcontrol si gnal ). %. ). %. ). 3%.3% 3%.3% 4(2%% 0(!3% -/4/2 -
application information L6230 18/24 doc id 18094 rev 2 figure 16. six-step with zero crossing detection typical application 6.4 thermal management in most applications the power dissipation in the ic is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. therefore, it has to be taken into account very carefully. besides the available space on the pcb, the right package should be chosen considering the power dissipation. heat sinking can be achieved using copper on the pcb with proper area and thickness. for instance, using a vfqfpn32l 5 x 5 package the typical r th(ja) is about 42 c/w when mounted on a double-layer fr4 pcb with a dissipating copper area of 0.5 cm 2 on the top side plus 6 cm 2 ground layer connected through 18 via holes (9 below the ic). otherwise, using a powerso package with copper slug soldered on a 1.5 mm copper thickness fr4 board with 6cm 2 dissipating footprint (copper thickness of 35 m), the r th(ja) is about 35c/w. using a multi-layer board with vias to a gr ound plane, thermal impedance can be reduced down to 15c/w. %. /54 #0 #0 '.$ #0/54 /54 /54 63 ! 0/7%2 '2/5.$ 3)'.!, '2/5.$ 6 3 6 $# 63 " 6#0 6"//4 # 0 # "//4 $ $ # # 3%.3% 2 3%.3% $)!'%. # %. 2 %. %.!",% ). %. ). %. ). %. :ero#rossing si gnal ). %. ). %. ). 3%.3% 3%.3% 4 (2%% 0(!3% -/4/2 - 2 2 2 2 2 2 2 2 2
L6230 package mechanical data doc id 18094 rev 2 19/24 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com . ecopack? is an st trademark. note: vfqfpn stands for thermally enhanced very thin profile fine pitch quad flat package no lead. very thin profile: 0.80 < a < 1.00 mm. details of terminal 1 are optional but must be located on the top surface of the package by using either a mold or marked features. table 9. vfqfpn 5 x 5 x 1.0, 32 lead, pitch 0.50 dim. databook (mm) min typ max a 0.80 0.85 0.95 b 0.18 0.25 0.30 b1 0.165 0.175 0.185 d 4.85 5.00 5.15 d2 3.00 3.10 3.20 d3 1.10 1.20 1.30 e 4.85 5.00 5.15 e2 4.20 4.30 4.40 e3 0.60 0.70 0.80 e0.50 l 0.30 0.40 0.50 ddd 0.08
package mechanical data L6230 20/24 doc id 18094 rev 2 figure 17. package dimensions
L6230 package mechanical data doc id 18094 rev 2 21/24 table 10. powerso36 mechanical data min. typ. max. a 3.6 a1 0.1 0.3 a2 3.3 a3 0 0.1 b 0.22 0.38 c 0.23 0.32 d (1) 15.8 16 d1 9.4 9.8 e 13.9 14.5 e 0.65 e3 11.05 e1 (1) 10.9 11.1 e2 2.9 e3 5.8 6.2 e4 2.9 3.2 g 0 0.1 h 15.5 15.9 h 1.1 l 0.8 1.1 n 10(max.) s 8 (max.)
package mechanical data L6230 22/24 doc id 18094 rev 2 figure 18. powerso36 mechanical drawings h d $ ( d 3620(& '(7$,/$ ' ( ( k[? '(7$,/$ ohdg voxj d 6 *djh3odqh / '(7$,/% '(7$,/% &23/$1$5,7< *& & 6($7,1*3/$1( h f 1 1 ? 0 $% e % $ + ( ' %277209,(:
L6230 revision history doc id 18094 rev 2 23/24 8 revision history table 11. document revision history date revision changes 14-oct-2010 1 first release 07-jun-2011 2 updated maturity status from preliminary data to final datasheet.
L6230 24/24 doc id 18094 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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